This invention relates to wet/dry etch techniques used during the process steps used in the manufacture of multilayered semiconductor circuit devices. During these process steps, it is desired to reduce field oxide bird's beak effect in active capacitor storage cells (referred to as "storage cells" in this disclosure) and to slightly trench the storage cell active area during a subsequent polysilicon etch.
Wet/dry etch refers to process steps in which selected areas on a silicon wafer are exposed by way of photolithography (photomasking) in order to remove (etch) the desired portion of these selected areas during the etching process. Wet etching uses acid chemical compounds in the liquid state, while dry etching use acid chemical compounds in the gaseous state. For example, preforming a wet etch step desired to remove an exposed nitride strip, a liquid made up of hot phosphoric acid is used to dissolve the nitride. As for the dry etch step, an exposed portion of polysilicon can be removed when presented with gaseous hydrofluoric acid.
The cause of field oxide bird's beak effect (bird's beak) initiates from process steps used to isolate an active area location of a storage cell. The Local Oxidation Of Silicon (LOCOS) process, a method commonly used to isolate storage cells in a memory array during the production of a semiconductor device (LSI, VLSI, etc.), constitutes the use of thick field oxide.
Initially, the silicon wafer is prepared using conventional process steps followed by growing a thin layer of initial oxide, usually silicon dioxide, over the wafer surface. Next, a layer of nitride is deposited on the wafer which is then patterned and etched away from all areas except those defined as storage cells. Field oxide is then grown over the areas that were not previously covered with nitride and as it grows it begins to encroach under the edge of the nitride layer.
This oxide encroachment under the nitride is known as bird's beak that results in the actual area of the storage cell being reduced after field oxidation is complete. Therefore, reducing bird's beak becomes a critical factor in increasing the capacitance of a storage cell by maximizing the cell's active area.
The invention relates to a technique to maximize storage cell active area in a high density/high volume semiconductor device fabrication process, such as for DRAMs (dynamic random access memories), by partially eliminating bird's beak without adding any process steps. The invention is applicable to all high density DRAM planar processes from the 16 Kbit to the 16 Megabit generations and beyond.
It is well known for high density DRAM process/cell design, that maximum storage cell active area must be obtained as a percentage of repeating geometry area in a DRAM array. This active region/repeating region ratio determines the overall die size for a given feature size capability. Maximized storage cell active area translates directly into lower cost per bit.
The storage cell active area must be large enough to insure proper sensing of data by the bitline sense amplifiers, to maintain data retention during the period of time before the cell is dynamically refreshed, and to insure strong immunity to single event upsets such as alpha particles.
As geometries shrink in more advanced generation DRAMs, bird's beak becomes a dominant limiting factor to the number of cells that can effectively be packed into a given die.